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| IN74ACT323 8-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER WITH PARALLEL I/O High-Speed Silicon-Gate CMOS The IN74ACT323 is identical in pinout to the LS/ALS323, HC/HCT323. The IN74ACT323 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The IN74ACT323 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a busoriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode-Select lines, S1 and S2, high. This places the outputs in the high-impedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low synchronous Reset overrides all other inputs. * TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A; 0.1 A @ 25C Outputs Source/Sink 24 mA ORDERING INFORMATION IN74ACT323N Plastic IN74ACT323DW SOIC TA = -40 to 85 C for all packages PIN ASSIGNMENT * * * * LOGIC DIAGRAM PIN 20=VCC PIN 10 = GND 1 IN74ACT323 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Sink/Source Current, per Pin mA 50 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TJ Junction Temperature (PDIP) TA Operating Temperature, All Package Types IOH Output Current - High IOL Output Current - Low t r, tf Input Rise and Fall Time * VCC =4.5 V VCC =5.5 V (except Schmitt Inputs) * VIN from 0.8 V to 2.0 V Min 4.5 0 Max 5.5 VCC 140 +85 -24 24 10 8.0 Unit V V C C mA mA ns/V -40 0 0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74ACT323 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed VCC Limits Symbol Parameter Test Conditions V 25 C -40C to 85C VOUT= 0.1 V or VCC-0.1 VIH Minimum High4.5 2.0 2.0 Level Input V 5.5 2.0 2.0 Voltage VOUT= 0.1 V or VCC-0.1 VIL Maximum Low 4.5 0.8 0.8 Level Input V 5.5 0.8 0.8 Voltage VOH Minimum High4.5 4.4 4.4 IOUT -50 A Level Output 5.5 5.4 5.4 Voltage * VIN=VIH or VIL 3.76 3.86 4.5 IOH=-24 mA 4.76 4.86 5.5 IOH=-24 mA VOL Maximum Low4.5 0.1 0.1 IOUT 50 A Level Output 5.5 0.1 0.1 Voltage * VIN= VIH or VIL 0.44 0.36 4.5 IOL=24 mA 0.44 0.36 5.5 IOL=24 mA IIN Maximum Input VIN=VCC or GND 5.5 0.1 1.0 Leakage Current 5.5 1.5 Additional Max. VIN=VCC - 2.1 V ICCT ICC/Input 5.5 IOZ Maximum Three- VIN (OE)= VIH or VIL 0.6 6.0 State Leakage VIN =VCC or GND Current VOUT =VCC or GND VOLD=1.65 V Max IOLD +Minimum 5.5 75 Dynamic Output Current VOHD=3.85 V Min IOHD +Minimum 5.5 -75 Dynamic Output Current VIN=VCC or GND ICC Maximum 5.5 8.0 80 Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Unit V V V V A mA A mA mA A 3 IN74ACT323 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Unit Symbol Parameter 25 C -40C to 85C Min Max Min Max fmax Maximum Clock Frequency (Figure 1) 120 110 MHz tPLH Propagation Delay, Clock to QA' or QH' 5.0 12.5 4.0 14.0 ns (Figure 1) tPHL Propagation Delay, Clock to QA' or QH' 5.0 13.5 4.5 15.0 ns (Figure 1) tPLH Propagation Delay, Clock to QA thru QH 5.0 12.5 4.5 13.5 ns (Figure 1) tPHL Propagation Delay, Clock to QA thru QH 6.0 15.0 5.0 16.5 ns (Figure 1) tPZH Propagation Delay , OE1, OE2 to QA thru 3.5 11.0 3.0 12.5 ns QH (Figure 3) tPZL Propagation Delay , OE1, OE2 to QA thru 3.5 11.5 3.0 13.0 ns QH (Figure 3) tPHZ Propagation Delay , OE1, OE2 to QA thru 4.0 12.5 3.0 13.5 ns QH (Figure 3) tPLZ Propagation Delay , OE1, OE2 to QA thru 3.0 11.5 2.5 12.5 ns QH (Figure 3) CIN Maximum Input Capacitance 4.5 4.5 pF Typical @25C,VCC=5.0 V 170 CPD Power Dissipation Capacitance pF TIMING REQUIREMENTS(VCC=5.0 V 10%, CL=50pF, Input tr=tf=3.0 ns) Guaranteed Limits Symb Parameter 25 C -40C ol to 85C tsu Minimum Setup Time, Mode Select S1 or S2 to Clock 5.0 5.0 (Figure 4) tsu Minimum Setup Time, Data Inputs PA thru PH to Clock 4.0 4.5 (Figure 4) tsu Minimum Setup Time, Data Inputs SA, SH to Clock 4.5 5.0 (Figure 4) tsu Minimum Setup Time, Reset to Clock (Figure 2) 2.5 2.5 th Minimum Hold Time, Clock to Mode Select S1 or S2 1.5 1.5 (Figure 4) th Minimum Hold Time, Clock to Data Inputs PA thru PH 1.0 1.0 (Figure 4) th Minimum Hold Time, Clock to Data Inputs SA, SH 1.0 1.0 (Figure 4) th Minimum Hold Time, Clock to Reset (Figure 2) 1.0 1.0 tw Minimum Pulse Width, Clock (Figure 1) 4.0 4.5 Unit ns ns ns ns ns ns ns ns ns 4 IN74ACT323 FUNCTION TABLE Inputs Response Mode Rese Mode Output Clock Serial PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA' QH' t Select Enables Inputs QA QB QC QD QE QF QG QH S2 S1 OE1 OE2 DA DH Reset L XL L L XXLLLLLLLL L L L LX L L XXLLLLLLLL L L L HH X X X XX QA through QH=Z L L Shift H LH H X D X Shift Right: QA through QH=Z; D QG Right DA FA; FA FB; etc H LH X H D X Shift Right: QA through QH=Z; D QG DA FA; FA FB; etc H LH L L DX Shift Right: DA FA =QA; D QG FA FB =QB; etc Shift H HL H X X D Shift Left: QA through QH=Z; QB D Left DH FH; FH FG; etc H HL X H X D Shift Left: QA through QH=Z; QB D DH FH; FH FG; etc H HL L L XD Shift Left: DH FH =QH; QB D FH FG =QG; etc Parallel H HH X X XX Parallel Load:PN FN PA PH Load Hold H LL H X X X X Hold: QA through QH=Z; FN=FN PA PH H LL X H X X X Hold: QA through QH=Z; FN=FN PA PH H LL L L X XX Hold: QN =QH PA PH Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. 5 IN74ACT323 Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform 6 IN74ACT323 EXPANDED LOGIC DIAGRAM 7 |
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